1. High-speed: a clock / machine cycle, the enhanced 8051 core, the speed is the normal 8051''s 8 to 12 times
2. Wide voltage design: 3.8 ~ 5.5V
3. Chip EEP ROM 5K, insert number 10 million times to write
4. Built-in hardware watchdog
5. Built-in reset system
6. There ISP / IAP, in-system programmable / programmable in the application without the need for programmer / emulator
7. 39 general I / O statement options
8. Three timer settings
9. Low-power design: Idle, Power-down wake-up support for 4 external interrupt, an interrupt can be arbitrary wake-up support falling edge / low voltage and remote wake-up
10. Operating frequency: 0 ~ 34MHz
11.56K bytes of on-chip Flash program memory, can be inserted more than 10 million times the number of write
12.4352 byte RAM data memory chip
